The present invention relates to controlling data flow in a data processor, and specifically in a graphics controller.
The ability of a data processor, such as a microcontroller, microprocessor, or graphics controller, to perform optimally is often limited by the rate at which data can be provided from a source external to the data processor. Recent industry trends toward Reduced Instruction Set Architectures (RISC) has increased the rate at which a data processors have been able to process data. Most general purpose high-end processors are capable of processing data at a data rate greater than external memory sources have been able to provide such data. When this happens, the data processor in effect stalls until the next data is available
When possible, applications that demand performance, use external memories capable of matching or exceeding the data width and size requirements of the data processor. Because of standard memory speeds, when memories are fast enough to meet the data rate of the microprocessor it is often necessary to use a memory capable of a greater data rate than is actually needed by the data processor. This allows the data processor to access the external memory on an as-needed basis. However, this wastes bandwidth of the associated data processor and increases costs. Therefore, it is desirable for a cost-effective scheme for utilizing the bandwidth of the memory, and providing the desired data to the data processor.